Archive for Task 5

Task 5

task5

Task description and Expected results
This task will be entirely devoted to the study and design of reconfigurable digital hardware components for the cognitive radio
transceiver baseband. The novelty of the approach consists in the exploration of innovative NC -OFDM hardware processing
architectures, partial run-time reconfiguration of the system and the on-line capability of designing optimized waveforms
employing custom modulations for each NC -OFDM sub-band. This task will be divided in two sub-tasks focusing on:
- flexible modulation schemes supporting fine grained run-time waveform design for advanced spectrum aggregation systems.
- high efficiency on-line reconfigurable NC -OFDM processing engines based on reconfigurable hardware architectures.
Sub-task 4.1 – Multimode NC -OFDM Processing Engine
The objective of this sub-task is to investigate and validate different approaches that can be used to implement a NC -OFDM
flexible transceiver supporting run-time selection of the active sub-carriers and modulation schemes for each sub-band. This will
allow the fine grained waveform design in spectrum aggregation scenarios based on NC -OFDM approaches while fulfilling
robustness, range, throughput and adaptability requirements.
The adoption of FPGAs as the implementation platform for symbol level processing of NC -OFDM systems allows the exploration
of hybrid hw/sw architectures, flexible integration, run-time adaptation and field upgrades of the transceiver parameters. In the
scope of this sub-task different architectures and implementation approaches will be explored in order to build a very flexible
and high performance NC -OFDM engine, such as, hybrid hardware/software approach based on a heterogeneous architecture
combining FPGA embedded processors enhanced by custom parallel hardware accelerators. Different architectural and
implementation aspects, figures of merit and trade-offs will be analyzed and compared, such as logic complexity, flexibility,
number of OFDM sub-carriers, bandwidth, performance, operating frequency, resource usage, power efficiency and cost.
number of OFDM sub-carriers, bandwidth, performance, operating frequency, resource usage, power efficiency and cost.
Two important aspects of any OFDM receiver implementation are the synchronization and channel equalization, both requiring
further research in the case of NC -OFDM systems due to the increased complexity.
Sub-task 4.2 – FPGA-based Fast Partial Dynamic Reconfiguration Approaches
Higher levels of system adaptability, upgradeability and efficiency can be achieved by means of dynamic partial reconfiguration
of FPGAs, i.e. selectively changing portions of the logic circuit implemented in the FPGA. The objective of this sub-task is to
introduce reconfiguration capacities into the platform for the symbol level processing of the C R transceiver. The reconfiguration
can be partial or complete. Besides its potential advantages in terms of hardware savings and configuration overhead, enabling
dynamic partial reconfiguration of the FPGA remains a challenge, because parts of the circuit logic need to be modified while the
rest of the device is working and processing data. An additional challenge consists in developing approaches to effectively
mitigate or eliminate the latency introduced by the reconfiguration process, both by exploiting configuration communalities and
by using intelligent pre-fetching.
FPGAs with embedded processors can execute Linux-like operating systems providing most of the required features to develop
the dynamic partial reconfiguration framework to manage the adaptability of the NC -OFDM transceiver following a modular
approach, allowing easier upgrades, code reuse and real-time online adaptability.
At the end of this sub-task it is expected that the state of the art will be advanced in the following points:
- Efficient NC -OFDM processing architectures enabling data throughputs compatible with next generation wireless communication
systems.
- Reduction of the reconfiguration times and reactivity improvement of C R transceivers.

Mem bers of the research team in this task: (BI) Bolseiro de Investigação (Mestre) 2; (BI) Bolseiro de Investigação (Mestre) 5; Arnaldo Silva Rodrigues de Oliveira; João
Nuno Pimentel da Silva Matos; João Paulo C astro C anas Ferreira; Manuel José Alves Ventura da Silva; Nelson José Valente da
Silva