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Standard Assignment of Signals to Pins |
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Optional Assignment of Signals to Pins |
Standard Assignment of Signals to Pins
Pin Number |
Signal Name |
Signal Standard |
1 |
GND |
0V |
2 |
INPUT1 |
TTL level, pulse input, pulse width >1 µs |
3 |
OUTPUT1 |
TTL level, latch output |
4 |
OUTPUT2 |
TTL level, latch output |
5 |
Output port A0 |
TTL level, latch output |
6 |
Output port A1 |
TTL level, latch output |
7 |
Output port A2 |
TTL level, latch output |
8 |
Output port A3 |
TTL level, latch output |
9 |
Output port A4 |
TTL level, latch output |
10 |
Output port A5 |
TTL level, latch output |
11 |
Output port A6 |
TTL level, latch output |
12 |
Output port A7 |
TTL level, latch output |
13 |
Output port B0 |
TTL level, latch output |
14 |
Output port B1 |
TTL level, latch output |
15 |
Output port B2 |
TTL level, latch output |
16 |
Output port B3 |
TTL level, latch output |
17 |
Output port B4 |
TTL level, latch output |
18 |
Output port B5 |
TTL level, latch output |
19 |
Output port B6 |
TTL level, latch output |
20 |
Output port B7 |
TTL level, latch output |
21 |
Input/output port C0 |
TTL level, latch output/input |
22 |
Input/output port C1 |
TTL level, latch output/input |
23 |
Input/output port C2 |
TTL level, latch output/input |
24 |
Input/output port C3 |
TTL level, latch output/input |
25 |
Input/output port D0 |
TTL level, latch output/input |
26 |
Input/output port D1 |
TTL level, latch output/input |
27 |
Input/output port D2 |
TTL level, latch output/input |
28 |
Input/output port D3 |
TTL level, latch output/input |
29 |
Port C status |
TTL level, Input mode: Low, Output mode: High |
30 |
Port D status |
TTL level, Input mode: Low, Output mode: High |
31 |
Write strobe signal |
TTL level, Negative logic, Pulse output |
32 |
(N/C) |
|
33 |
PASS/FAIL signal |
TTL level, PASS: High, FAIL: Low |
34 |
+5 V |
+5 V, 100 mA maximum |
35 |
SWEEP END signal |
TTL level, Negative logic, Pulse output (width>10µs) |
36 |
PASS/FAIL write strobe signal |
TTL level, Negative logic, Pulse output |
Return to Rear Panel
Optional Assignment of Signals to Pins
Pin Number |
Signal Name |
Signal Standard |
1 |
GND |
0V |
2 |
INPUT1 |
TTL level, pulse input, (width >1 µs) |
3 |
OUTPUT1 |
TTL level, latch output |
4 |
OUTPUT2 |
TTL level, latch output |
5 |
Output port A0 |
TTL level, latch output |
6 |
Output port A1 |
TTL level, latch output |
7 |
Output port A2 |
TTL level, latch output |
8 |
Output port A3 |
TTL level, latch output |
9 |
Output port A4 |
TTL level, latch output |
10 |
Output port A5 |
TTL level, latch output |
11 |
Output port A6 |
TTL level, latch output |
12 |
Output port A7 |
TTL level, latch output |
13 |
Output port B0 |
TTL level, latch output |
14 |
Output port B1 |
TTL level, latch output |
15 |
Output port B2 |
TTL level, latch output |
16 |
Output port B3 |
TTL level, latch output |
17 |
Output port B4 |
TTL level, latch output |
18 |
Not used |
|
19 |
Output port B5 |
TTL level, latch output |
20 |
Output port B6 |
TTL level, latch output |
21 |
Output port B7 |
TTL level, latch output |
22 |
Input/output port C0 |
TTL level, latch output/input |
23 |
Input/output port C1 |
TTL level, latch output/input |
24 |
Input/output port C2 |
TTL level, latch output/input |
25 |
Input/output port C3 |
TTL level, latch output/input |
26 |
Input/output port D0 |
TTL level, latch output/input |
27 |
Input/output port D1 |
TTL level, latch output/input |
28 |
Input/output port D2 |
TTL level, latch output/input |
29 |
Input/output port D3 |
TTL level, latch output/input |
30 |
Port C status |
TTL level, Input mode: Low, Output mode: High |
31 |
Port D status |
TTL level, Input mode: Low, Output mode: High |
32 |
Output port write strobe |
TTL level, Negative logic, Pulse output |
33 |
PASS/FAIL signal |
TTL level, PASS: High, FAIL: Low |
34 |
SWEEP END signal |
TTL level, Negative logic, Pulse output (width>10µs) |
35 |
+5 V |
+5 V, 100 mA maximum |
36 |
PASS/FAIL write strobe |
TTL level, Negative logic, Pulse output |
Return to Rear Panel |