The following files were generated for 'mig_v3_4' in directory 
C:\ml605_mig_design\

mig_v3_4\docs\ds186.pdf:
   Please see the core data sheet.

mig_v3_4\docs\ug406.pdf:
   Please see the core data sheet.

mig_v3_4_flist.txt:
   Text file listing all of the output files produced when a customized
   core was generated in the CORE Generator.

mig_v3_4\example_design\datasheet.txt:
   Please see the core data sheet.

mig_v3_4\example_design\log.txt:
   Please see the core data sheet.

mig_v3_4\example_design\mig.prj:
   Please see the core data sheet.

mig_v3_4\example_design\par\bitgen_options.ut:
   Please see the core data sheet.

mig_v3_4\example_design\par\constraints.xcf:
   Please see the core data sheet.

mig_v3_4\example_design\par\create_ise.bat:
   Please see the core data sheet.

mig_v3_4\example_design\par\example_top.cdc:
   Please see the core data sheet.

mig_v3_4\example_design\par\example_top.ucf:
   Please see the core data sheet.

mig_v3_4\example_design\par\icon5_cg.xco:
   CORE Generator input file containing the parameters used to
   regenerate a core.

mig_v3_4\example_design\par\ila384_8_cg.xco:
   CORE Generator input file containing the parameters used to
   regenerate a core.

mig_v3_4\example_design\par\ise_flow.bat:
   Please see the core data sheet.

mig_v3_4\example_design\par\makeproj.bat:
   Please see the core data sheet.

mig_v3_4\example_design\par\readme.txt:
   Please see the core data sheet.

mig_v3_4\example_design\par\rem_files.bat:
   Please see the core data sheet.

mig_v3_4\example_design\par\set_ise_prop.tcl:
   Please see the core data sheet.

mig_v3_4\example_design\par\vio_async_in256_cg.xco:
   CORE Generator input file containing the parameters used to
   regenerate a core.

mig_v3_4\example_design\par\vio_sync_out32_cg.xco:
   CORE Generator input file containing the parameters used to
   regenerate a core.

mig_v3_4\example_design\par\xst_options.txt:
   Please see the core data sheet.

mig_v3_4\example_design\rtl\controller\arb_mux.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\controller\arb_row_col.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\controller\arb_select.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\controller\bank_cntrl.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\controller\bank_common.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\controller\bank_compare.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\controller\bank_mach.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\controller\bank_queue.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\controller\bank_state.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\controller\col_mach.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\controller\mc.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\controller\rank_cntrl.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\controller\rank_common.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\controller\rank_mach.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\controller\round_robin_arb.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\ecc\ecc_buf.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\ecc\ecc_dec_fix.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\ecc\ecc_gen.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\ecc\ecc_merge_enc.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\ip_top\clk_ibuf.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\ip_top\ddr2_ddr3_chipscope.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\ip_top\example_top.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\ip_top\infrastructure.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\ip_top\iodelay_ctrl.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\ip_top\mem_intfc.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\ip_top\memc_ui_top.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\phy\circ_buffer.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\phy\phy_ck_iob.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\phy\phy_clock_io.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\phy\phy_control_io.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\phy\phy_data_io.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\phy\phy_dly_ctrl.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\phy\phy_dm_iob.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\phy\phy_dq_iob.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\phy\phy_dqs_iob.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\phy\phy_init.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\phy\phy_pd.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\phy\phy_pd_top.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\phy\phy_rdclk_gen.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\phy\phy_rdctrl_sync.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\phy\phy_rddata_sync.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\phy\phy_rdlvl.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\phy\phy_read.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\phy\phy_top.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\phy\phy_write.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\phy\phy_wrlvl.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\phy\rd_bitslip.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\traffic_gen\afifo.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\traffic_gen\cmd_gen.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\traffic_gen\cmd_prbs_gen.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\traffic_gen\data_prbs_gen.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\traffic_gen\init_mem_pattern_ctr.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\traffic_gen\mcb_flow_control.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\traffic_gen\mcb_traffic_gen.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\traffic_gen\pipeline_inserter.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\traffic_gen\rd_data_gen.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\traffic_gen\read_data_path.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\traffic_gen\read_posted_fifo.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\traffic_gen\sp6_data_gen.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\traffic_gen\tg_status.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\traffic_gen\v6_data_gen.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\traffic_gen\wr_data_gen.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\traffic_gen\write_data_path.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\ui\ui_cmd.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\ui\ui_rd_data.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\ui\ui_top.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\rtl\ui\ui_wr_data.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\sim\glbl.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\sim\isim_files.prj:
   Please see the core data sheet.

mig_v3_4\example_design\sim\isim_options.tcl:
   Please see the core data sheet.

mig_v3_4\example_design\sim\isim_run.bat:
   Please see the core data sheet.

mig_v3_4\example_design\sim\readme.txt:
   Please see the core data sheet.

mig_v3_4\example_design\sim\sim.do:
   Please see the core data sheet.

mig_v3_4\example_design\sim\sim_tb_top.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\sim\wiredly.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\example_design\synth\example_top.lso:
   Please see the core data sheet.

mig_v3_4\example_design\synth\example_top.prj:
   Please see the core data sheet.

mig_v3_4\example_design\synth\synplify_pro.tcl:
   Please see the core data sheet.

mig_v3_4\user_design\datasheet.txt:
   Please see the core data sheet.

mig_v3_4\user_design\log.txt:
   Please see the core data sheet.

mig_v3_4\user_design\mig.prj:
   Please see the core data sheet.

mig_v3_4\user_design\par\bitgen_options.ut:
   Please see the core data sheet.

mig_v3_4\user_design\par\constraints.xcf:
   Please see the core data sheet.

mig_v3_4\user_design\par\create_ise.bat:
   Please see the core data sheet.

mig_v3_4\user_design\par\icon5_cg.xco:
   CORE Generator input file containing the parameters used to
   regenerate a core.

mig_v3_4\user_design\par\ila384_8_cg.xco:
   CORE Generator input file containing the parameters used to
   regenerate a core.

mig_v3_4\user_design\par\ise_flow.bat:
   Please see the core data sheet.

mig_v3_4\user_design\par\makeproj.bat:
   Please see the core data sheet.

mig_v3_4\user_design\par\mig_v3_4.cdc:
   Please see the core data sheet.

mig_v3_4\user_design\par\mig_v3_4.ucf:
   Please see the core data sheet.

mig_v3_4\user_design\par\readme.txt:
   Please see the core data sheet.

mig_v3_4\user_design\par\rem_files.bat:
   Please see the core data sheet.

mig_v3_4\user_design\par\set_ise_prop.tcl:
   Please see the core data sheet.

mig_v3_4\user_design\par\vio_async_in256_cg.xco:
   CORE Generator input file containing the parameters used to
   regenerate a core.

mig_v3_4\user_design\par\vio_sync_out32_cg.xco:
   CORE Generator input file containing the parameters used to
   regenerate a core.

mig_v3_4\user_design\par\xst_options.txt:
   Please see the core data sheet.

mig_v3_4\user_design\rtl\controller\arb_mux.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\controller\arb_row_col.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\controller\arb_select.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\controller\bank_cntrl.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\controller\bank_common.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\controller\bank_compare.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\controller\bank_mach.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\controller\bank_queue.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\controller\bank_state.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\controller\col_mach.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\controller\mc.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\controller\rank_cntrl.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\controller\rank_common.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\controller\rank_mach.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\controller\round_robin_arb.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\ecc\ecc_buf.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\ecc\ecc_dec_fix.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\ecc\ecc_gen.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\ecc\ecc_merge_enc.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\ip_top\clk_ibuf.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\ip_top\ddr2_ddr3_chipscope.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\ip_top\infrastructure.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\ip_top\iodelay_ctrl.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\ip_top\mem_intfc.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\ip_top\memc_ui_top.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\ip_top\mig_v3_4.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\phy\circ_buffer.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\phy\phy_ck_iob.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\phy\phy_clock_io.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\phy\phy_control_io.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\phy\phy_data_io.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\phy\phy_dly_ctrl.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\phy\phy_dm_iob.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\phy\phy_dq_iob.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\phy\phy_dqs_iob.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\phy\phy_init.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\phy\phy_pd.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\phy\phy_pd_top.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\phy\phy_rdclk_gen.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\phy\phy_rdctrl_sync.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\phy\phy_rddata_sync.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\phy\phy_rdlvl.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\phy\phy_read.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\phy\phy_top.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\phy\phy_write.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\phy\phy_wrlvl.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\phy\rd_bitslip.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\ui\ui_cmd.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\ui\ui_rd_data.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\ui\ui_top.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\rtl\ui\ui_wr_data.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\sim\afifo.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\sim\cmd_gen.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\sim\cmd_prbs_gen.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\sim\data_prbs_gen.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\sim\glbl.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\sim\init_mem_pattern_ctr.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\sim\isim_files.prj:
   Please see the core data sheet.

mig_v3_4\user_design\sim\isim_options.tcl:
   Please see the core data sheet.

mig_v3_4\user_design\sim\isim_run.bat:
   Please see the core data sheet.

mig_v3_4\user_design\sim\mcb_flow_control.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\sim\mcb_traffic_gen.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\sim\pipeline_inserter.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\sim\rd_data_gen.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\sim\read_data_path.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\sim\read_posted_fifo.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\sim\readme.txt:
   Please see the core data sheet.

mig_v3_4\user_design\sim\sim.do:
   Please see the core data sheet.

mig_v3_4\user_design\sim\sim_tb_top.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\sim\sp6_data_gen.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\sim\tg_status.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\sim\v6_data_gen.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\sim\wiredly.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\sim\wr_data_gen.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\sim\write_data_path.v:
   Verilog wrapper file provided to support functional simulation.
   This file contains simulation model customization data that is
   passed to a parameterized simulation model for the core.

mig_v3_4\user_design\synth\mig_v3_4.lso:
   Please see the core data sheet.

mig_v3_4\user_design\synth\mig_v3_4.prj:
   Please see the core data sheet.

mig_v3_4\user_design\synth\synplify_pro.tcl:
   Please see the core data sheet.

mig_v3_4.gise:
   ISE Project Navigator support file. This is a generated file and should
   not be edited directly.

mig_v3_4.veo:
   VEO template file containing code that can be used as a model for
   instantiating a CORE Generator module in a Verilog design.

mig_v3_4.xco:
   CORE Generator input file containing the parameters used to
   regenerate a core.

mig_v3_4.xise:
   ISE Project Navigator support file. This is a generated file and should
   not be edited directly.

mig_v3_4_readme.txt:
   Text file indicating the files generated and how they are used.

mig_v3_4_xmdf.tcl:
   ISE Project Navigator interface file. ISE uses this file to determine
   how the files output by CORE Generator for the core can be integrated
   into your ISE project.


Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.

