

CORE Generator Options:
   Target Device                 : xc6vlx240t-ff1156
   Speed Grade                   : -1
   HDL                           : verilog
   Synthesis Tool                : XST

MIG Output Options:
   Module Name                   : mig_v3_4
   No of Controllers             : 1
   Selected Compatible Device(s) : --
   Hardware Test Bench           : enabled

FPGA Options:
   Clock Type                    : Differential
   Debug Port                    : ON
   Internal Vref                 : disabled

Extended FPGA Options:
   DCI for DQ,DQS/DQS#,DM        : enabled
   DCI for Address/Control       : enabled
    
/*******************************************************/
/*                  Controller 0                       */
/*******************************************************/
Controller Options :
   Memory                 : DDR3_SDRAM
   Design Clock Frequency : 2500 ps (400.00 MHz)
   Memory Type            : SODIMMs
   Memory Part            : MT4JSF6464HY-1G1
   Equivalent Part(s)     : --
   Data Width             : 64
   ECC                    : Disabled
   Data Mask              : enabled
   ORDERING               : Strict

Memory Options:
   Burst Length (MR0[1:0])          : 8 - Fixed
   Read Burst Type (MR0[3])         : Sequential
   CAS Latency (MR0[6:4])           : 6
   Write Recovery (MR0[11:9])       : 5
   Output Drive Strength (MR1[5,1]) : RZQ/7
   Rtt_NOM - ODT (MR1[9,6,2])       : RZQ/4
   Rtt_WR - Dynamic ODT (MR2[10:9]) : Dynamic ODT off

FPGA Options:
   IODELAY PERFORMANCE MODE : HIGH

Selected Banks and Pins usage : 
       Data          :bank 25(40) -> Number of pins used : 35 
                      bank 26(40) -> Number of pins used : 35 
                      bank 35(40) -> Number of pins used : 24 
                      
       Address/Control:bank 36(40) -> Number of pins used : 25 
                      
       System Clock  :bank 34(40) -> Number of pins used : 9 
                      
       Master Banks  :bank 25(40) 
       VRN/VRP       :bank 25(40) -> Number of pins used : 2 
                      bank 35(40) -> Number of pins used : 2 
                      bank 36(40) -> Number of pins used : 2 
                      
       VREF          :bank 25(40) -> Number of pins used : 2 
                      bank 26(40) -> Number of pins used : 2 
                      bank 35(40) -> Number of pins used : 2 
                      bank 36(40) -> Number of pins used : 1 
                      
       BUFR          :bank 26(40) -> Number of pins used : 1 
                      bank 36(40) -> Number of pins used : 1 
                      
       BUFIO         :bank 25(40) -> Number of pins used : 3 
                      bank 26(40) -> Number of pins used : 3 
                      bank 35(40) -> Number of pins used : 2 
                      
       Total IOs used :    144



    