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//*****************************************************************************
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: 3.4
//  \   \         Application: MIG
//  /   /         Filename: phy_clock_io.v
// /___/   /\     Date Last Modified: $Date: 2010/02/26 08:58:33 $
// \   \  /  \    Date Created: Aug 03 2009
//  \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
//Purpose:
//   Top-level for CK/CK# clock forwarding to memory
//Reference:
//Revision History:
//*****************************************************************************

/******************************************************************************
**$Id: phy_clock_io.v,v 1.3 2010/02/26 08:58:33 pboya Exp $
**$Date: 2010/02/26 08:58:33 $
**$Author: pboya $
**$Revision: 1.3 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/M/mig_v3_4/data/dlib/virtex6/ddr3_sdram/verilog/rtl/phy/phy_clock_io.v,v $
******************************************************************************/

`timescale 1ps/1ps

module phy_clock_io #
  (
   parameter TCQ          = 100,       // clk->out delay (sim only)
   parameter CK_WIDTH     = 2,         // # of clock output pairs
   parameter WRLVL        = "OFF",     // Enable write leveling
   parameter DRAM_TYPE    = "DDR3",    // Memory I/F type: "DDR3", "DDR2"
   parameter REFCLK_FREQ  = 300.0,     // IODELAY Reference Clock freq (MHz)
   parameter IODELAY_GRP  = "IODELAY_MIG"  // May be assigned unique name
                                              // when mult IP cores in design
   )
  (
   input                 clk_mem,   // full rate core clock
   input                 clk,       // half rate core clock
   input                 rst,       // half rate core clk reset
   output [CK_WIDTH-1:0] ddr_ck_p,  // forwarded diff. clock to memory
   output [CK_WIDTH-1:0] ddr_ck_n   // forwarded diff. clock to memory
   );

  //***************************************************************************

  generate
    genvar ck_i;
    for (ck_i = 0; ck_i < CK_WIDTH; ck_i = ck_i + 1) begin: gen_ck
      phy_ck_iob #
        (
         .TCQ            (TCQ),
         .WRLVL          (WRLVL),
         .DRAM_TYPE      (DRAM_TYPE),
         .REFCLK_FREQ    (REFCLK_FREQ),
         .IODELAY_GRP    (IODELAY_GRP)
         )
        u_phy_ck_iob
          (
           .clk_mem   (clk_mem),
           .clk       (clk),
           .rst       (rst),
           .ddr_ck_p  (ddr_ck_p[ck_i]),
           .ddr_ck_n  (ddr_ck_n[ck_i])
           );
    end
  endgenerate

endmodule
